This invention relates to storage control method and apparatus for a computer system, especially, being suitable for operating a plurality of access request control units synchronously in parallel and ensuring the sequence or order between access requests which are sequentially issued to a storage area.
In conventional storage controlling, access requests are issued from a plurality of access request control units to a storage comprised of a plurality of independently accessible memory units (memory banks) as will be described below with reference to FIG. 1.
Referring to FIG. 1, access request control units 20A to 20D are sources for issuing access requests. Access request stack units 21A to 21D respectively stack access requests issued from each of the access request control units 20A to 20D. Each of the stack units sends a stacked access request in the order of stacking, to one of access request priority deciders 22A to 22D in accordance with address information contained in that access request. A storage area 23 is comprised of memory banks 23A to 23D.
Taking the access request control unit 20A, for instance, access requests issued from the unit 20A are stacked in a stack circuit 211 of the access request stack unit 21A and under the direction of a control circuit 210, a stacked access request is sent to one of the access request priority deciders 22A to 22D corresponding to one memory bank which is designated by an address contained in that access request. Each access request priority decider 22A, 22B, 22C or 22D selects one of the access requests sent from the access request stack units 21A to 21D and sends a selected access request to the storage area 23. The selection may be accomplished pursuant to priority grading which is predetermined among the access requests. The priority grading may be changed desirably to treat the access requests from the access request stack units as equally as possible. For example, the access request stack units 21A to 21D may be graded in the order of 21A, 21B, 21C and 21D for the initial concurrent access cycle, in the order of 21B, 21C, 21D and 21A for the next concurrent access cycle and in the order of 21C, 21D, 21A and 21B for the concurrent access cycle after next.
In another example, the order of 21A, 21B, 21C and 21D and the order of 21D, 21C, 21B and 21A may be repeated alternately for the purpose of the equal treatment.
It is thus regulated that a plurality of access requests be applied to one decider, for example, 22A at a time and access requests be sent serially one by one from the decider to one memory bank, for example, 23A.
Taking the access request priority decider 22A, for instance, a priority decision logic 220 checks and decides the access requests sent from the access request stack units 21A to 21D to the decider 22A for their priority and transmits a selected one of the access requests to the memory bank 23A of the storage 23. The other access requests not selected at that time are urged to wait at the entrance to the priority decision logic 220.
The access requests are transmitted from the access request control unit 20A until the stack 211 of the access request stack unit 21A fills up. When a control circuit 221 of, for example, the decider 22A transmits a signal 213 indicative of the fact that an access request 212 issued during the preceding machine cycle (a periodical predetermined interval of time during which a group of sequential circuits constituting the system operate synchronously) is selected by the logic 220 and the stack unit 21A receives the signal 213, the succeeding access request 212 is sent from the stack unit 21A. This warrants that in the order of the access requests issued from the access request control unit 20A, accessed data elements can be read out of the storage 23.
In addition to the prior art storage control apparatus described above, another storage control apparatus has been proposed as disclosed in JP-A-No. 60-136849, according to which with a view to improve the performance of the entire system, access requests to be issued from an access request control unit are divided, in the order of issuance, into groups each having a access requests (a is an integer) in unit whereby a access requests in each group are respectively added with access request identifiers 0 to (a-1) and then are issued from the access request control unit, and an access request priority decider directly coupled to a memory unit selects an access request and returns an access request identifier for the selected access request to the access request control unit which is an originator.
Incidentally, a vector processor for fast processing of a scientific computation comprises a plurality of vector registers for holding vector data, a plurality of arithmetic units for operating on the data, and a plurality of access request control units for data transfer between a storage and each of the vector registers, whereby vector elements in one vector instruction are concurrently allocated to a plurality of resources, such as vector registers, arithmetic units or access request control units, and are processed in parallel. Such parallel processing is a so-called element parallel processing mode and has been employed frequently in vector processors.
Generally speaking, it is desirable that the resources in the same group operating concurrently in the element parallel processing mode by completely synchronized with each other to process the allocated elements. By the complete synchronization, a control circuit can be used in common for the plurality of resources in the same group operating in parallel, thereby simplifying the control logic. In this approach, there arises however a problem that a waiting time takes place owing to competition for accessing to memory bank constituting the storage. Accordingly, in order for the plurality of resources in the same group to operate synchronously with each other, the advent of a storage control apparatus is desired which can absorb asynchonism occurring between the resources on account of the waiting time to thereby completely synchronize the storage accessing.
Reviewing then the prior art storage control apparatus disclosed in JP-A-No. 60-136849 mentioned previously, it will be seen that this prior art apparatus presupposes the fact that one access instruction is processed by allocating it to a single access request control unit and fails to take into consideration a processing in which data elements treated by one vector access instruction are divided for allotment to a plurality of access request control units with the aim of being processed in parallel, thus resulting in the problem that the plurality of access request control units to be operated in parallel can not be synchronized with each other so as to process access requests.